A CMOS image sensor transforms optical images to electrical signals using CMOS technologies. The CMOS image sensor employs a switching method that sequentially generates signals using MOS transistors. The CMOS image sensor has several advantages such as a simple operation process, low fabrication costs and low power consumption. On the contrary, a charge coupled device (CCD) image sensor is difficult to fabricate compared to the CMOS image sensor and impossible to access randomly. Since the late 1990s, fabrication methods of CMOS technologies and signal processing algorithms thereof have been improved. Therefore, many disadvantages of the CMOS have been overcome. Moreover, the CCD technology has been partially employed in the CMOS image sensor, so that product qualities of the CMOS image sensor have been further improved.
FIG. 1 is a schematic circuit diagram of a typical CMOS image sensor 100. Referring to FIG. 1, the typical CMOS image sensor 100 includes a photodiode Pd, a transfer transistor Tx, a reset transistor Rx, a selection transistor Sx and an access transistor Ax. The transfer transistor Tx and the reset transistor Rx are connected in serial to the photodiode Pd. An applied voltage Vdd is supplied to a drain of the reset transistor Rx. A drain of the transfer transistor Tx (i.e., a source of the reset transistor Rx) corresponds to a floating diffusion layer (F/D). The floating diffusion layer (F/D) is connected to a gate of the selection transistor Sx. The selection transistor Sx and the access transistor Ax are connected in serial and an applied voltage Vdd is supplied to a drain of the selection transistor Sx.
An operation method of the CMOS image sensor 100 will be explained as follows. First, the reset transistor Rx is turned on, so that a voltage of the floating diffusion layer (F/D) becomes the applied voltage Vdd. If light is incident to the photodiode Pd, electron-hole pairs (EHPs) are generated and signal electrons are accumulated in a source of the transfer transistor Tx. When the transfer transistor Tx is turned on, the accumulated signal electrons are transferred to the floating diffusion layer (F/D) to change a voltage of the floating diffusion layer (F/D). At same time, a gate voltage of the selection transistor Sx changes to the voltage of the floating diffusion layer. When a selection signal Row turns on the access transistor Ax, the applied voltage Vdd is transferred to an output terminal Out. Then, the reset transistor Rx is turned on again and the voltage of the floating diffusion layer (F/D) is made equal to the applied voltage Vdd. Through repeating these steps, image signals are generated.
FIG. 2 is a top plan view of a typical CMOS image sensor. Referring to FIG. 2, the CMOS image sensor includes a device isolation pattern 56 that is formed in a substrate to define a diode region 40 and an active region 42. Conventionally, the diode region 40 is formed to be wide so as to increase a photo efficiency. The active region 42 is extended from a side of the diode region 40. Transfer gates 64 and 24, reset gates 66 and 26 and selection gates 68 and 28 are serially formed and separated by a predetermined distance. Although not illustrated in the drawings, an access gate is formed separate from the selection gates 68 and 28 by a predetermined distance. The transfer gate Tx is formed in the active region 42 adjacent to the diode region 40. Floating diffusion layers 70 and 38 are formed in the active region 42 between the transfer gates 64 and 24 and the reset gates 66 and 26. Although not illustrated in the drawings, the floating diffusion layers 70 and 38 and the selection gate 68 and 28 are electrically connected through interconnections.
FIGS. 3 and 4 are cross-sectional views taken along line A-A of FIG. 2 for illustrating steps of fabricating a conventional CMOS image sensor. Referring to FIG. 3, a deep P well 12 is formed in a semiconductor substrate. The deep P well 12 may be formed in a substrate between a P type epitaxial layer 10a and a silicon substrate 10. By implanting impurities into the P type epitaxial layer 10a, a P well 14 is formed in the P type epitaxial layer 10a. The P well 14 is formed adjoining a diode region 40 of FIG. 2 that will be defined in a subsequent process. A device isolation pattern 16 of FIG. 2 is formed to define an active region 42 of FIG. 2 and the diode region 40 of FIG. 2. An N type channel diffusion layer 22 is formed in an active region 42 of FIG. 2 adjacent to the diode region 40 of FIG. 2. A transfer gate 24, a reset gate 26 and a selection gate 28 are serially formed on the active region 42 of FIG. 2 separated from each other. The transfer gate 24 is formed on the N type channel diffusion layer 22. Impurities are implanted into the diode region 40 of FIG. 2 to form an N type photodiode 18. A P type photodiode 20 is formed on the N type photodiode 18. The N type and P type photodiodes 18 and 20 may be formed prior to forming the gates.
Next, the impurities are implanted into the active region 42 of FIG. 2 to form lightly doped diffusion layers 30 and 32 aligned to sidewalls of the transfer, reset and selection gates 24, 26 and 28.
Referring to FIG. 4, an insulation layer is formed on an entire surface of the substrate with the lightly doped diffusion layers 30 and 32. A photoresist pattern is formed to cover the diode region 40 of FIG. 2 and expose the active region 42 of FIG. 2. Next, using the photoresist as an etch mask, the insulation layer is anisotropically etched to form a blocking layer 34a covering the diode region 40 of FIG. 2 and sidewall spacers 34b on sidewalls of the transfer gate 24, the reset gate 26 and the selection gate 28. Then, the photoresist is removed. In the conventional CMOS image sensor, the blocking layer 34a covers the diode region 40 of FIG. 2 and is extended in a lateral direction to conformally cover a portion of a top surface and a sidewall of the transfer gate 24. Using the blocking layer 34a, the gates 24, 26 and 28 and the sidewall spacers 34b as an etching mask, impurities are implanted into the substrate to form heavily doped diffusion layers 36, which are aligned to outer edges of the sidewall spacers 34b, in the lightly doped diffusion layers 30 and 32. As a result, diffusion layers with a DDD (double doped drain) structure are formed in the active region 42 of FIG. 2. Alternatively, diffusion layers with a LDD (lightly doped drain) structure may be formed in the active region 42 of FIG. 2. The lightly and heavily doped diffusion layers 30 and 36 between the transfer gate 24 and the reset gate 26 compose a floating diffusion layer 38 of an image sensor.
According to the prior art, after covering the diode region 40 of FIG. 2, the insulation layer is etched anisotropically, so that a surface of the P type photodiode 20 may be protected from being attacked. Therefore, a dark current can be drastically reduced at a surface of the P type photodiode 20. However, during a formation of the sidewall spacers 34b, a surface of the active region, where the floating diffusion layer 38 is formed, may be damaged from etching and crystalline defects of the active region can occur due to high energy of the ions during the formation of the heavily doped diffusion layers 36. Therefore, a leakage current pass is created at the floating diffusion layer 38, so that a voltage of the floating diffusion layer 38 may not be increased. As a result, output signals may be leveled down or not be generated. In addition, if the diffusion is formed to have an LDD structure, the floating diffusion layer 38 will have a large probability of suffering from a leakage current due to a high voltage between the heavily doped diffusion layers 36 and the P well 14.